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256K x 16-Bit EDO-Dynamic RAM
HYB 514265BJ-400/40/-45/-50 HYB 314265BJ(L)-45/-50
Preliminary Information
* * * *
262 144 words by 16-bit organization 0 to 70 C operating temperature EDO - Hyper Page Mode Performance: -400 -40 69 40 10 20 15 66 -45 79 45 12 22 18 55 -50 89 50 13 25 20 50 ns ns ns ns ns MHz
*
Power Supply: HYB 514265BJ-400 HYB 514265BJ-40 HYB 514265BJ-45 HYB 514265BJ-50 +5 V +5 V +5 V +5 V 5% 10% 10% 10%
HYB 314265BJ(L)-45 +3.3 V 0.3 V HYB 314265BJ(L)-50 +3.3 V 0.3 V Read, write, read-modify-write, CAS -before RAS refresh, RAS only refresh, hidden refresh mode * Low Power Version (L) with Self Refresh and 250 A self refresh current
* *
trc trac tcac taa thpc thpc
*
69 40 10 20 12,5 80
2 CAS / 1 WE control All inputs and outputs TTL-compatible 512 refresh cycles / 16 ms 512 refresh cycles / 128 ms (L-version) Plastic Packages: P-SOJ-40-3 400 mil width
Low Power dissipation - Active(max.): 120mA / 120mA / 105mA / 95 mA - Standby : TTL Inputs (max.) 2.0 mA - Standby: CMOS Inputs (max.) 1.0 mA - Standby (L-version) 200 A
* *
*
The HYB 5(3)14265BJ(L) is the new generation dynamic RAM organized as 262 144 words by 16-bit. The HYB 5(3)14265BJ(L) utilizes the SIEMENS 16M-CMOS submicron silicon gate process as well as advanced circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)14265BJ(L) to be packed in a standard plastic 400mil wide P-SOJ-40-3 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. The HYB314265BJL parts have a very low power "sleep mode" supported by Self Refresh.
Semiconductor Group
1
6.96
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Ordering Information Type
5 V versions: HYB 514265BJ-400 HYB 514265BJ-40 HYB 514265BJ-45 HYB 514265BJ-50 3.3 V versions: HYB 314265BJ-45 HYB 314265BJ-50 HYB 314265BJL-45 HYB 314265BJL-50 on request on request on request on request P-SOJ-40-3 P-SOJ-40-3 P-SOJ-40-3 P-SOJ-40-3 3.3 V 45 ns 256 K x 16 EDO- DRAM 3.3 V 50 ns 256 K x 16 EDO- DRAM 3.3 V Low Power 45 ns 256 K x 16 EDO- DRAM 3.3 V Low Power 50 ns 256 K x 16 EDO-DRAM Q67100-3033 Q67100-3039 Q67100-3035 Q67100-3036 P-SOJ-40-3 P-SOJ-40-3 P-SOJ-40-3 P-SOJ-40-3 5 V 40 ns 256 K x 16 EDO-DRAM 5 V 40 ns 256 K x 16 EDO-DRAM 5 V 45 ns 256 K x 16 EDO-DRAM 5 V 50 ns 256 K x 16 EDO-DRAM
Ordering Code
Package
Description
Truth Table RAS H L L L L L L L L LCAS H H L H L L H L L UCAS H H H L L H L L L WE H H H H H L L L H OE H H L L L H H H H I/O1-I/O8 High-Z High-Z Dout High-Z Dout Din Don't care Din High-Z I/O9-I/O16 High-Z High-Z High-Z Dout Dout Don't care Din Din High-Z Operation Standby Refresh Lower byte read Upper byte read Word read Lower byte write Upper byte write Word write
Pin Names A0-A8 RAS UCAS, LCAS WE OE I/O1 - I/O16 Address Inputs Row Address Strobe Column Address Strobe Read/Write Input Output Enable Data Input/Output Power Supply: + 5 V for HYB 514265, + 3.3 V for HYB 314265 Ground (0 V) No Connection
VCC
VSS
N.C.
Semiconductor Group
2
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Pin Configuration (top view)
P-SOJ-40-3
Semiconductor Group
3
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Block Diagram
Semiconductor Group
4
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Absolute Maximum Ratings Operating temperature range ........................................................................................ 0 to + 70 C Storage temperature range..................................................................................... - 55 to + 150 C Input/output voltage for HYB 514265................................................ - 0.5 to min. (VCC + 0.5, 7.0) V Power supply voltage for HYB 514265 ........................................................................... - 1 to + 7 V Input/output voltage for HYB 314265................................................ - 0.5 to min. (VCC + 0.5, 4.6) V Power supply voltage for HYB 314265 ..................................................................... - 0.5 to + 4.6 V Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics for HYB514265 TA = 0 to 70 C; VSS = 0 V; VCC = 5 V 10 % ( 5 % for -400 version) , tT = 2 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5.0 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current, any input (0 V < VIN < 7 V, all other inputs = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < VCC) Average VCC supply current: -400 version -40 version -45 version -50 version Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
Symbol
VIH VIL VOH VOL II(L) IO(L) ICC1
Limit Values min. max. 2.4 VCC + 0.5 - 0.5 0.8 2.4 - - 0.4 - 10 10 - 10 - 120 120 105 95 2 10
Unit Notes V V V V A A
1 1 1 1 1 1
mA
2, 3, 4
ICC2 ICC3
- -
mA
-
Average VCC supply current during RAS-only refresh cycles: -400 version -40 version -45 version -50 version
120 120 105 95
mA
2, 4
Semiconductor Group
5
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Parameter Average VCC supply current during hyper page mode (EDO) operation: -400 version -40 version -45 version -50 version Standby VCC supply current
(RAS = LCAS = UCAS = WE = VCC - 0.2 V)
Symbol
ICC4
ICC5 ICC5 ICC6
Limit Values min. max. - 110 90 75 65 - 1 - - 120 120 105 95 200
Unit Notes
mA
2, 3, 4
mA A
1 1
Standby VCC supply current (L-version only)
(RAS = LCAS = UCAS = WE = VCC - 0.2 V)
Average VCC supply current during CAS-before-RAS refresh mode: -400 version -40 version -45 version -50 version
mA
2, 4
DC Characteristics for 314265 TA = 0 to 70 C; VSS = 0 V; VCC = 3.3 V 0.3 V, tT = 2 ns Parameter Input high voltage Input low voltage TTL Output high voltage (IOUT = - 2.0 mA) TTL Output low voltage (IOUT = 2 mA) CMOS Output high voltage (IOUT = - 100 A) CMOS Output low voltage (IOUT = 100 A) Input leakage current, any input
(0 V < VIN <
Symbol
Limit Values min. max. 0.8 - 0.4 - 0.4 10 10 2.0 - 0.5 2.4 - 2.4 - - 10 - 10 - 105 95
Unit Test Condition
1 1 1 1 1 1 1 1
VIH VIL VOH VOL VOH VOL II(L) IO(L) ICC1
-45 version -50 version
VCC + 0.5 V
V V V V V A A
VCC + 0.3 V, all other inputs = 0 V)
Output leakage current
(DO is disabled, 0 V < VOUT < VCC + 0.3 V)
Average VCC supply current:
mA
2, 3, 4
Standby VCC supply current
(RAS = LCAS = UCAS = WE = VIH)
ICC2
-
2
mA
-
Semiconductor Group
6
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Parameter Average VCC supply current during RAS-only refresh cycles: -45 version -50 version
Symbol
Limit Values min. max. -
Unit Test Condition mA
2, 4
ICC3
105 95
Average VCC supply current during hyper page ICC4 mode (EDO) operation: -45 version -50 version Standby VCC supply current
(RAS = LCAS = UCAS = WE = VCC - 0.2 V)
- mA 75 65 - - - mA 105 95 - 250 A
2, 4 2, 3, 4
ICC5 ICC5
1 200
mA A
1 1
Standby VCC supply current (L-version only)
(RAS = LCAS = UCAS = WE = VCC - 0.2 V)
Average VCC supply current during CASbefore-RAS refresh mode: ICC6 -45 version -50 version Self Refresh Current (L-version only)
CBR cycle with RAS >trasss(min), CAS held low; WE = VCC - 0.2 V, Addresses and Din = VCC - 0.2 V or 0.2 V
ICC7
Capacitance TA = 0 to 70 C; f = 1 MHz Parameter Input capacitance (A0 to A8) Input capacitance (RAS, UCAS, LCAS, WE, OE) Output capacitance (l/O1 to l/O16) Symbol Limit Values min. max. 5 7 7 pF pF pF - - - Unit
CI1 CI2 CIO
Semiconductor Group
7
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
AC Characteristics 5) 6) TA = 0 to 70 C, tT = 2 ns Parameter
Symbol
Limit Values -400 min. max. min. -40 max.
Unit Note
Common Parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delaytime RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time(rise and fall) Refresh period
tRC tRP tRAS tCAS tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF
69 25 40 4.5 4 0 5 0 5 9 7 6 32 5 1 16
- - 10k 10k - - - - - 30 20 - - - 50 -
69 25 40 6 5 0 5 0 5 9 7 6 32 5 1 16
- - 10k 10k - - - - - 30 20 - - - 50 -
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms
7
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time ref. to RAS CAS to output inlow-Z Output buffer turn-off delay from CAS
tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ tOFF
- - - - 20 0 0 0 0 0
40 10 17 10 - - - - - -
- - - - 20 0 0 0 0 0
40 10 20 10 - - - - - 10
ns ns ns ns ns ns ns ns ns ns
8, 9 8, 9 8,10
11 11 8 12
Semiconductor Group
8
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Parameter
Symbol
Limit Values -400 min. max. 10 - - - - min. 0 0 8 8 0 - - - -40 max. 10
Unit Note
Output buffer turn-off delay from OE Data to OE low delay CAS high to data delay OE high to data delay Data to CAS low delay
tOEZ tDZO tCDD tODD tDZC
0 0 8 8 0
ns ns ns ns ns
12 13 14 14 13
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time Data to CAS low delay
tWCH tWP tWCS tRWL tCWL tDS tDH tDZC
5 5 0 10 10 0 5 0
- - - - - - - -
5 5 0 10 10 0 5 0
- - - - - - - -
ns ns ns ns ns ns ns ns
16 16 13 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time
tRWC tRWD tCWD tAWD tOEH
93 52 22 32 5
- - - - -
93 52 22 32 5
- - - - -
ns ns ns ns ns
15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode cycle time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode RAS hold time from CAS precharge
tHPC tCPA tCOH tRAS tRHCP
12.5 - 3 40 17
- 17 - 200k -
15 - 3 40 21
- 21 - 200k -
ns ns ns ns ns
7
Semiconductor Group
9
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Parameter
Symbol
Limit Values -400 min. max. min. -40 max.
Unit Note
Hyper Page Mode (EDO) Read-Modify-Write Cycle
Hyper page mode read/write cycle time CAS precharge to WE delay time
tPRWC tCPWD
55 35
- -
55 35
- -
ns ns
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write to RAS hold time
tCSR tCHR tRPC tWRP tWRH
5 5 5 10 10
- - - - -
5 5 5 10 10
- - - - -
ns ns ns ns ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
25
-
25
-
ns
Semiconductor Group
10
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
AC Characteristics 5)6) TA = 0 to 70 C, tT = 2 ns Parameter
Symbol
16E
Limit Values -45 min. max. min. -50 max.
Unit Note
Common Parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width CAS precharge time Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period Refresh period (L-version only)
tRC tRP tRAS tCAS tCP tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF tREF
79 30 45 7 7 0 7 0 7 11 9 12 36 5 1 - -
- - 10k 10k - - - - - 33 23
89 35 50 8 8 0 8 0 8 12 10 13 40
- - 10k 10k - - - - - 37 25 - - - 50 16 128
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 7
- 50 16 128
5 1 - -
Read Cycle
Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z
tRAC tCAC tAA tOEA tRAL tRCS tRCH tRRH tCLZ
- - - - 23 0 0 0 0
45 12 22 12 - - - - -
- - - - 25 0 0 0 0
50 13 25 13 - - - - -
ns ns ns ns ns ns ns ns ns
8, 9 8, 9 8,10
11 11 8
Semiconductor Group
11
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, tT = 2 ns Parameter
Symbol
16E
Limit Values -45 min. max. 12 12 - - - - min. 0 0 0 0 10 10 -50 max. 13 13 - - - -
Unit Note
Output buffer turn-off delay Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay
tOFF tOEZ tDZC tDZO tCDD tODD
0 0 0 0 10 10
ns ns ns ns ns ns
12 12 13 13 14 14
Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time
tWCH tWP tWCS tRWL tCWL tDS tDH
7 7 0 12 12 0 7
- - - - - - -
8 8 0 13 13 0 8
- - - - - - -
ns ns ns ns ns ns ns 16 16 15
Read-modify-Write Cycle
Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time
tRWC tRWD tCWD tAWD tOEH
107 59 26 36 7
- - - - -
118 64 27 39 10
- - - - -
ns ns ns ns ns 15 15 15
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time Access time from CAS precharge Output data hold time RAS pulse width in EDO mode CAS precharge to RAS Delay
tHPC tCPA tCOH tRAS tRHPC
18 - 5 45 25
- 25 - 200k -
20 - 5 50 27
- 27 - 200k -
ns ns ns ns ns 7
Semiconductor Group
12
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
AC Characteristics (cont'd) 5)6) TA = 0 to 70 C, tT = 2 ns Parameter
Symbol
16E
Limit Values -45 min. max. min. -50 max.
Unit Note
Hyper Page Mode (EDO) Read-modify-Write Cycle
Hyper page mode (EDO) read-write cycle time tPRWC CAS precharge to WE 51 41 - - 58 41 - - ns ns
tCPWD
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS
tCSR tCHR tRPC tWRP tWRH
5 10 5 10 10
- - - - -
10 10 5 10 10
- - - - -
ns ns ns ns ns
CAS-before-RAS Counter Test Cycle
CAS precharge time
tCPT
30
-
35
-
ns
Self Refresh Cycle (L-version)
RAS pulse width RAS precharge CAS hold time
tRASS tRPS tCHS
100k 110 - 50
- - -
100k 95 - 50
- - -
ns ns ns
17 17 17
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = VIL. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 2 ns.
Semiconductor Group
13
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 50 pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tAA, tCPA , tOEA. tCAC is measured from tristate .
+ 1.5 V 50 Ohm Z=50 Ohm I/O 50 pF
fig.2 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.), tOEZ (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) Either tDZC or tDZO must be satisfied. 14) Either tCDD or tODD must be satisfied. 15) tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.) and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of I/O (at access time) is indeterminate. 16) These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles.
17)When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh.
Semiconductor Group
14
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Read Cycle Semiconductor Group 15
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Write Cycle (Early Write)
Semiconductor Group
16
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Write Cycle (OE Controlled Write)
Semiconductor Group
17
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Read-Write (Read-Modify-Write) Cycle
Semiconductor Group
18
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Hyper Page Mode (EDO) Read Cycle
Semiconductor Group
19
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Hyper Page Mode (EDO) Early Write Cycle
Semiconductor Group
20
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Hyper Page Mode (EDO) Late Write and Read-Modify-Write Cycles
Semiconductor Group
21
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
RAS-Only Refresh Cycle
Semiconductor Group
22
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
CAS-Before-RAS Refresh Cycle
Semiconductor Group
23
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
CAS before RAS Self Refresh Cycle
Semiconductor Group
24
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Hidden Refresh Cycle (Read)
Semiconductor Group
25
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Hidden Refresh Cycle (Early Write)
Semiconductor Group
26
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
CAS-Before-RAS Refresh Counter Test Cycle
Semiconductor Group
27
HYB 5(3)14265BJ(L)-400/-40/-45/-50 256K x 16 EDO-DRAM
Package Outlines P-SOJ-40-3 (Small Outline J-Leaded Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 28
Dimensions in mm
GPJ09018

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